MercorVerified Source
RemoteOtherAI & Machine Learning

RTL Design Engineers | $100-$175/hr Remote

$100–$175/hr
Posted June 28, 2026
full-time

Overview

Obsidian is hiring experienced senior digital chip design engineers to contribute to an AI evaluation program focused on cutting-edge silicon workflows. This remote role offers a competitive hourly rate and the chance to work on frontier semiconductor design projects. Candidates can choose between an RTL Design track or a Design Verification track, both requiring deep technical expertise and a commitment to high-quality hardware engineering.

What You'll Do5

  • 1Develop and optimize RTL modules using Verilog/SystemVerilog, covering finite state machines, data paths, pipelines, and bus interfaces.
  • 2Perform synthesis, timing analysis, and CDC (Clock Domain Crossing) checks to ensure design integrity and manufacturability.
  • 3Debug hardware issues using simulation logs and waveform viewers, collaborating closely with verification and architecture teams.
  • 4Write clear design documentation and communicate technical trade-offs to cross-functional groups.
  • 5Leverage LLM-based tools to accelerate RTL development, debugging, and documentation workflows.

Requirements5

  • 13–10 years of hands-on experience in digital RTL design for ASIC flows, with strong proficiency in Verilog or SystemVerilog.
  • 2Solid grasp of digital design fundamentals including FSMs, clock domains, arbiters, and bus protocols.
  • 3Familiarity with EDA tools for simulation, waveform debug, lint, synthesis, and timing analysis.
  • 4Experience using LLM-based tools to streamline chip design tasks such as RTL generation, debug, or documentation.
  • 5Strong collaboration skills and the ability to work across architecture, verification, and implementation teams.

Who Should Apply

This role is ideal for a seasoned digital chip design engineer who thrives in a fast-paced, remote environment and is excited about applying LLM-assisted workflows to hardware development. If you have a deep understanding of ASIC design flows, enjoy solving complex timing and logic challenges, and can commit to a focused 3+ month engagement, you'll be a great fit.

Salary Insight

Hourly rate ranges from $100 to $175 per hour, depending on experience and expertise.

Application Tip

Highlight any experience you have using LLMs (like ChatGPT or Copilot) to assist with RTL coding, debugging, or documentation — it's a key differentiator for this program.

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