ASIC/SoC Design & Verification Engineer | $70-$100/hr Remote
Overview
A top-tier AI lab is assembling a remote team of experienced chip engineers to help train and evaluate their most advanced AI models. In this part-time role, you'll draw on your real-world ASIC and SoC design or verification experience to create authentic engineering challenges—from RTL architecture to timing closure—that push the boundaries of what AI can understand. If you've been hands-on with silicon that made it to tapeout, this is a chance to bring that practical judgment directly into the heart of AI development.
What You'll Do4
- 1Craft realistic chip engineering problems based on your own project experience—think real-world debugging, design trade-offs, and verification scenarios, not textbook exercises.
- 2Develop complete reference solutions for those problems, including SystemVerilog / Verilog RTL, testbenches, and supporting collateral using the industry tools you already know.
- 3Run your problems against the lab's AI models, analyze where they succeed or fail, and provide clear feedback to improve model reasoning.
- 4Collaborate with fellow engineers to ensure all problems and solutions meet a consistently high bar of technical rigor and difficulty.
Requirements6
- 1Proven hands-on experience in ASIC / SoC design or functional verification, preferably with production silicon that has successfully taped out.
- 2Strong fluency in SystemVerilog and Verilog; comfortable working with industry-standard tools like Synopsys VCS, Cadence Xcelium, Siemens Questa, or open-source alternatives such as Verilator, CocoTB, and Yosys.
- 3Solid understanding of subsystem- and SoC-level concerns, including interface protocols, handshaking, multiple clock domains, and multi-module dataflow.
- 4Deep expertise in at least one specialized area: RTL design & microarchitecture; IP integration (NoC, PCIe, DDR, ARM/AXI); functional verification using UVM, SVA, or CocoTB; formal verification & coverage closure; PPA/timing/synthesis optimization; analog/mixed-signal verification; or specification authoring and Q&A.
- 5Ability to commit 20–40 hours per week with a consistent schedule and no conflicts.
- 6Excellent written communication and the ability to work independently; prior experience in AI training, model evaluation, or data annotation is a plus.
Who Should Apply
This role is perfect for a seasoned chip engineer who thrives on practical problem-solving and wants to apply their hard-won knowledge to improve AI reasoning. You should be comfortable working autonomously, communicating clearly in writing, and collaborating with a distributed team of like-minded experts. If you've ever wished your real-world debugging and design judgment could inform how AI learns, this is the opportunity.
Salary Insight
The position pays $70.00–$100.00 per hour on a part-time W-2 basis through Cincinnatus LLC, with a commitment of 20–40 hours per week.
Application Tip
When applying, emphasize specific tapeout projects you've contributed to—mention the technology node, your role in RTL design or verification, and any metrics like timing closure or coverage results. If you've worked with AI models or curated training data before, be sure to highlight that experience.
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