Chip Design Expert (RTL Design & Verification)

What You'll Do6

• Read each task end to end: the specification, the starting files, the reference solution and the test suite.
• Confirm the reference solution passes and that every check in the tests follows from what the spec states.
• Flag defects such as vague specs, tests that accept a broken design or reject a correct one, leaked answers, and tasks that look harder than they are.
• Judge whether the difficulty level still troubles the best AI models available.
• Write precise feedback with concrete fixes the task authors can act on.
• Propose new task ideas and help shape early drafts into reviewable problems.

Requirements5

• 5+ years of hands-on RTL design or verification work in industry, whether semiconductor, FPGA, EDA or a related field.
• Strong Verilog and SystemVerilog skills.
• Practical experience with simulation and testbench construction.
• Ability to read Python test code and reason about what it actually checks.
• Review habits built on skepticism and care, plus clear written explanations of why a task fails.

Preferred Qualifications3

• Experience with open-source EDA tools such as Icarus Verilog, Verilator, Yosys or cocotb
• Formal verification background
• Prior work reviewing benchmarks for AI models

Who Should Apply

Hardware engineers with 5+ years of RTL design or verification work who spot a broken testbench fast and explain the flaw in writing. The schedule suits someone who wants part-time remote review work alongside a current role or research.

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